Performance Predictions for Speculative, Synchronous, VLSI Logic Simulation
نویسندگان
چکیده
VLSI logic simulation is an application area in which execution time improvements can have direct economic benefits. Here, we investigate the use of parallel simulation techniques to improve the performance of VLSI logic simulation, including the often neglected issue of sensitivity to variations in the simulation workload. Performance predictions are presented for the use of speculative computation in synchronous discrete-event simulation of VLSI systems.
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